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3/98 features precision fault threshold programmable: average power limiting, linear current control, overcurrent limit and fault time fault output indication signal automatic retry mode or latched operation mode shutdown control undervoltage lockout 250 m s glitch filter on the sdfltch pin 8-pin dil and soic latchable negative floating hot swap power manager block diagram ucc1921 ucc2921 ucc3921 udg-99052 description the ucc3921 family of negative floating hot swap power managers pro- vides complete power management, hot swap, and fault handling capa- bility. the ic is referenced to the negative input voltage and is powered through an external resistor connected to ground, which is essentially a current drive as opposed to the traditional voltage drive. the onboard 10v shunt regulator protects the ic from excess voltage and serves as a reference for programming the maximum allowable output sourcing cur- rent during a fault. all control and housekeeping functions are integrated and externally programmable. these include the fault current level, maxi- mum output sourcing current, maximum fault time, selection of retry or latched mode, soft start time, and average power limiting. in the event of a constant fault, the internal timer will limit the on time from less than 0.1% to a maximum of 3% duty cycle. the duty cycle modulation de- pends on the current into pl, which is a function of the voltage across the fet, thus limiting average power dissipation in the fet. the fault level is fixed at 50mv across the current sense amplifier to minimize total (continued)
2 ucc1921 ucc2921 ucc3921 electrical characteristics unless otherwise specified, t a = 0c to 70c for the ucc3921 and C40c to 85c for the ucc2921, and C55c to 125c for the ucc1921; i vdd = 2ma, c t = 1nf (the minimum allowable value), there is no resistor connected between the sdfltch and vss pins. t a =t j . parameter test conditions min typ max units vdd section idd 12ma regulator voltage i source = 2ma 9 9.5 10.0 v i source = 10ma 9.15 9.6 10.15 v uvlo off voltage 67 8 v fault timing section overcurrent threshold t j = 25c 47.5 50 53.5 mv over operating temperature 46 50 53.5 mv overcurrent input bias 50 500 na ct charge current v ct = 1v, i pl = 0 C50 C36 C22 m a overload condition, v sense -v imax = 300mv C1.7 C1.2 C0.7 ma ct discharge current v ct = 1v, i pl = 0 0.6 1 1.5 m a ct fault threshold 2.2 2.45 2.6 v ct reset threshold 0.41 0.49 0.57 v output duty cycle fault condition, i pl = 0 1.7 2.7 3.7 % connection diagram dil-8 , soic-8 (top view) norj,dpackages absolute maximum ratings i vdd .......................................... 50ma sdfltch current .............................. 10ma pl current .................................... 10ma imax input voltage ..............................vdd storage temperature ................... - 65c to +150c junction temperature ................... C55c to +150c lead temperature (soldering, 10 sec.) ............. +300c all voltages are with respect to v ss (the most negative voltage). currents are positive into, negative out of the specified terminal. consult packaging section of databook for thermal limitations and considerations of packages. dropout. the fault current level is set with an external current sense resistor, while the maximum allowable sourcing current is programmed with a voltage divider from vdd to generate a fixed voltage on imax. the cur- rent level, when the output acts as a current source, is equal to v imax /r sense . if desired, a controlled current start up can be programmed with a capacitor on imax. when the output current is below the fault level, the out- put device is switched on. when the output current ex- ceeds the fault level, but is less than the maximum sourcing level programmed by imax, the output remains switched on, and the fault timer starts charging c t . once c t charges to 2.5v, the output device is turned off and performs a retry some time later (provided that the se- lected mode of operation is automatic retry mode). when the output current reaches the maximum sourcing current level, the output acts as a current source, limiting the output current to the set value defined by imax. other features of the ucc3921 include undervoltage lockout, 8-pin small outline (soic) and dual-in-line (dil) packages, and a latched operation mode option, in which the output is latched off once c t charges to 2.5v and stays off until either sdfltch is toggled (for greater than 1ms) or the ic is powered down and then back up. description (continued)
3 ucc1921 ucc2921 ucc3921 electrical characteristics unless otherwise specified, t a = 0c to 70c for the ucc3921 and C40c to 85c for the ucc2921, and C55c to 125c for the ucc1921; i vdd = 2ma, c t = 1nf (the minimum allowable value), there is no resistor connected between the sdfltch and vss pins. t a =t j . parameter test conditions min typ max units output section output high voltage i out = 0ma 8.5 10 v i out = C1ma 6 8 v output low voltage i out = 0ma, v sense Cv imax = 100mv 0 10 mv i out = 2ma, v sense Cv imax = 100mv 200 600 mv linear amplifier section sense control voltage v imax = 100mv 85 100 115 mv v imax = 400mv 370 400 430 mv input bias 50 500 na power limiting section v sense regulator voltage i pl =64 m a 4.35 4.85 5.35 v duty cycle control i pl =64 m a 0.6 1.2 1.7 % i pl = 1ma 0.045 0.1 0.17 % overload section delay to output note 1 300 500 ns output sink current v sense Cv imax = 300mv 40 100 ma threshold relative to imax 140 200 260 mv shutdown/fault/latch section shutdown threshold 3 5 vdd+1 v input current v sdfltch = 5v 50 110 250 m a filter delay time (delay to output) 250 500 1000 m s fault output high 6 9.5 v i sdfltch = C100 m a 5 8.5 v fault output low 010mv output duty cycle fault condition, i pl = 0 1.7 2.7 3.7 % i sdfltch = C100 m a, fault condition, i pl =0 0 % note 1: guaranteed by design. not 100% tested in production. pin descriptions ct: a capacitor is connected to this pin in order to set the fault time. the fault time must be longer than the time to charge external load capacitance. the fault time is defined as: t c i fault t ch = 2 where i ch =36 m a+i pl , and i pl is the current into the power limit pin. once the maximum fault time is reached the output will shutdown for a time given by: tc sd t = 210 6 imax: this pin programs the maximum allowable sourcing current. since vdd is a regulated voltage, a voltage divider can be derived from vdd to generate the program level for imax. the current level at which the output appears as a current source is equal to the voltage on imax over the current sense resistor. if desired, a controlled current start up can be programmed with a capacitor on imax, and a programmed start delay can be achieved by driving the shutdown with an open collector/drain device into an rc network. out: this pin provides gate output drive to the mosfet pass element. pl: this feature ensures that the average mosfet power dissipation is controlled. a resistor is connected from this pin to the drain of the nmos pass element. when the voltage across the nmos exceeds 5v, current will flow into the pl pin which adds to the fault timer charge current, reducing the duty cycle from the 3% level. when i pl >>36 m a, then the average mosfet power dissipation is given by: p avg imax r mosfet pl = - 110 6
4 ucc1921 ucc2921 ucc3921 figure 1. fault timing circuitry for the ucc3921, including power limit overload application information udg-96275-1 sense: input voltage from the current sense resistor. when there is greater than 50mv across this pin with respect to vss, then a fault is sensed, and c t starts to charge. sdfltch: this pin provides fault output indication, shutdown control, and operating mode selection. interface into and out of this pin is usually performed through level shift transistors. when open, and under a non-fault condition, this pin pulls to a low state with respect to vss. when a fault is detected by the fault timer, or undervoltage lockout, this pin will drive to a high state with respect fo vss, indicating the nmos pass element is off. when > 250 m a is sourced into this pin for > 1ms, it drives high causing the output to disable the nmos pass device. if an 5k < r latch < 250k w resistor is placed from this pin to vss, then the latched operating mode will be invoked. upon the occurrence of a fault, under the latched mode of operation, once the c t capacitor charges up to 2.5v the nmos pass element latches off. a retry will not periodically occur. to reset the latched off device, either sdfltch is toggled high for a duration greater than 1ms or the ic is powered down and then up. vdd: current driven with a resistor to a voltage approxi- mately 10v more positive than vss. typically a resistor is connected to ground. the 10v shunt regulator clamps vdd approximately 10v above vss, and is also used as an output reference to program the maximum allowable sourcing current. vss: ground reference for the ic and the most negative voltage available. pin descriptions (continued)
5 ucc1921 ucc2921 ucc3921 figure 2. retry operation mode udg-96276 t0: safe condition. output current is nominal, output voltage is at the negative rail, vss. t1: fault control reached. output current rises above the programmed fault value, ct begins to charge at ~36 m a. t2: maximum current reached. output current reaches the programmed maximum level and becomes a con- stant current with value i max . t3: fault occurs. ct has charged to 2.5v, fault output goes high, the fet turns off allowing no output current to flow, v out floats up to ground. t4: retry. ct has discharged to 0.5v, but fault current is still exceeded, ct begins charging again, fet is on, v out pulled down towards vss. t5 = t3: illustrates 3% duty cycle. t6 = t4: retry. ct has discharged to 0.5v, but fault is still exceeded, ct begins charging again, fet is on, v out pulled down towards vss. t7: output short circuit. if v out is short circuited to ground, ct charges at a higher rate depending upon the values for vss and r pl . t8: fault occurs. output is still short circuited, but the occurrence of a fault turns the fet off so no current is conducted. t9 = t4: output short circuit released, still in fault mode. t10 = t0: fault released, safe condition. return to nor- mal operation of the hot swap power manager. application information (continued) figure 1 shows the detailed circuitry for the fault timing function of the ucc3921. for the time being, we will dis- cuss a typical fault mode, therefore, the overload com- parator, and current source i3 does not work into the operation. once the voltage across the current sense re- sistor, r s , exceeds 50mv, a fault has occurred. this causes the timing capacitor to charge with a combination of 36 m a plus the current from the power limiting amplifier. the pl amplifier is designed to only source current into the ct pin and to begin sourcing current once the volt- age across the output fet exceeds 5v. the current i pl is related to the voltage across the fet with the following expression: i vv r pl fet pl = - 5 where v fet is the voltage across the nmos pass device. later it will be shown how this feature will limit average power dissipation in the pass device. note that under a condition where the output current is more than the fault level, but less than the max level, v out ? vss (input voltage), i pl = 0, the ct charging current is 36 m a.
6 ucc1921 ucc2921 ucc3921 figure 3. latched operation mode: r latch = 82k application information (cont.) udg-96277 t0: safe condition. output current is nominal, output voltage is at the negative rail, vss. t1: fault control reached. output current rises above the programmed fault value, ct begins to charge at ~36 m a. t2: maximum current reached. output current reaches the programmed maximum level and becomes a con- stant current with value i max . t3: fault occurs. ct has charged to 2.5v, fault output goes high as indicated by the sdfltch voltage. the fet turns off allowing no output current to flow, v out floats up to ground, and since there is an 82k w resistor from the sdfltch pin to vss, the internal latchset sig- nal goes high. t4: since the user does not want the chip to latch off during this cycle, he toggles sdfltch high for greater than 1ms {t6 - t4 > 1ms}. t5: the latchset signal is reset. t6: forcing of sdfltch is released after having been applied for > 1ms. t7: retry (since the latchset signal has been reset to its low state) - ct has discharged to 0.5v, but fault current is still exceeded, ct begins charging again, fet is on, v out pulled down towards vss. t8 = t3: fault occurs. ct has charged to 2.5v, fault out- put goes high as indicated by the sdfltch voltage, the fet turns off allowing no output current to flow, v out floats up to ground, and since there is an 82k w resistor from sdfltch to vss, the internal latchset signal goes high. t9: output is latched off. even though ct has dis- charged to 0.5v, there will not be a retry since the latchset signal was allowed to remain high. t10: output remains latched off. ct has discharged all thewayto0v. t11: the output has been latched off for quite some time. the user now wishes to reset the latched off out- put, thus toggling sdfltch high for greater than 1ms {t13 - t11}. t12 = t5: the latchset signal is reset. t13: forcing of sdfltch is released after having been applied for > 1ms. the fault had also been released during the time the output was latched off, safe condi- tion, return to normal operation of the hot swap power manager.
7 ucc1921 ucc2921 ucc3921 during a fault, ct will charge at a rate determined by the internal charging current and the external timing capaci- tor. once ct charges to 2.5v, the fault comparator switches and sets the fault latch. setting of the fault latch causes both the output to switch off and the charging switch to open. ct must now discharge with the 1 m a cur- rent source, i2, until 0.5v is reached. once the voltage at ct reaches 0.5v, the fault latch resets, which re-enables the output and allows the fault circuitry to regain control of the charging switch. if a fault is still present, the fault comparator will close the charging switch causing the cy- cle to repeat. under a constant fault, the duty cycle is given by: duty cycle a ia pl = + 1 36 m m average power dissipation in the pass element is given by: pvi a ia fet fet max pl avg = + 1 36 m m where v fet >>5v i pl can be approximated as: v r fet pl and where i pl >>36 m a, the duty cycle can be approxi- mated as : 1 m ar v pl fet therefore, the maximum average power dissipation in the mosfet can be approximated by: pvi ar v imax a r fet fet max pl fet pl avg = = 1 1 m m notice that in the approximation, v fet cancels, thereby limiting the average power dissipation in the nmos pass element. overload comparator the linear amplifier in the ucc3921 ensures that the output nmos does not pass more than i max (which is v imax/ r sense ). in the event the output current exceeds the programmed i max by 0.2v/r sense, which can only occur if the output fet is not responding to a command from the ic, ct will begin charging with i3, 1ma, and continue to charge to approximately 8v. this allows a constant fault to show up on the sdfltch pin, and also since the voltage on ct will continue charging past 2.5v in an overload fault mode, it can be used for detection of output fet failure or to build redundancy into the sys- tem. determining external component values to set r vdd (see fig. 4) the following must be achieved: v r v rr ma in vdd min > + + 10 12 2 in order to estimate the minimum timing capacitor, c t , several things must be taken into account. for example, given the schematic in figure 4 as a possible (and at this point, a standard) application, certain external compo- nent values must be known in order to estimate c tmin . now, given the values of c out , load, r sense ,v ss , and the resistors determining the voltage on the imax pin, the user can calculate the approximate startup time of the node v out. this startup time must be faster than the time it takes for c t to charge to 2.5v (relative to v ss ), and is the basis for estimating the minimum value of c t . in order to determine the value of the sense resistor, r sense , assuming the user has determined the fault cur- rent, r sense can be calculated by: r mv i sense fault = 50 next, the variable i max must be calculated. i max is the maximum current that the ucc3921 will allow through the transistor, m1, and it can be shown that during startup with an output capacitor the power mosfet, m1, can be modeled as a constant current source of value i max where i v r max imax sense = where v imax = voltage on pin imax. given this information, calculation of the startup time is now possible via the following: application information (continued) figure 4. udg-96278
8 ucc1921 ucc2921 ucc3921 current source load: t cv ii start out ss max load = - resistive load: t cr n ir ir v start out out max out max out ss = - ? ? ? ? ? l once t start is calculated, the power limit feature of the ucc3921 must be addressed and component values de- rived. assuming the user chooses to limit the maximum allowable average power that will be associated with the hot swap power manager, the power limiting resistor, r pl , can be easily determined by the following: r pavg ai pl fet max = 1 m where a minimum r pl exists defined by r v ma pl ss min = 5 (refer to figure 5). finally, after computing the aforementioned variables, the minimum timing capacitor can be derived as such: current source load: () c tarvv r t start pl ss pl min = +- 372 10 10 m resistive load: () c tarvvir r r t start pl ss max out pl o min = +-- + 336 5 5 3 m ut ss out pl vc r 5 level shift circuitry to interface with sdfltch some type of circuit is needed to interface with the ucc3921 via sdfltch, such as opto-couplers or level shift circuitry. figure 6 depicts one implementation of level shift circuitry that could be used, showing compo- nent values selected for a typical C48v telecommunica- tions application. there are three communication conditions which could occur; two of which are hot swap power manager (hspm) state output indications, and the third being an external shutdown. 1) when open, and under a non-fault condition, sdfltch is pulled to a low state. in figure 6, the n- channel level shift transistor is off, and the fault out signal is pulled to local vdd through r3. this indicates that the hspm is not faulted. 2) when a fault is detected by the fault timer or under- voltage lockout, this pin will drive to a high state, indi- cating that the external power fet is off. in figure 6, the n-channel level shift transistor will conduct, and the fault out signal will be pulled to a schottky di- ode voltage drop below local gnd. this indicates that the hspm is faulted. the schottky diode is nec- essary to ensure that the fault out signal does not traverse too far below local gnd, making fault detection difficult. application information (continued) 25 22.5 20 17.5 15 12.5 10 7.5 5 2.5 0 0 25 50 75 100 125 150 175 200 v fet r r pl pl =500k =200k r pl =1m r pl =2m r pl =5m r pl =10m r pl= i=4a max = figure 5. plot average power vs fet voltage for increasing values of r pl figure 6. possible level shift circuitry to interface to the ucc3921, showing component values selected for a typical telecom application. udg-96279 =
9 ucc1921 ucc2921 ucc3921 if a5k 250 m a into sdfltch for > 1ms the output to the external power fet will be dis- abled. the current sourced into sdfltch must be limited to 10ma or less: i sdfltchmax < 10ma. safety recommendations although the ucc3921 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. for this reason, if the ucc3921 is intended for use in safety critical applications where ul or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the external power fet. the ucc3921 will prevent the fuse from blowing for virtually all fault conditions, in- creasing system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device. application information (continued) w figure 7. typical telecommuications application (the negative magnitude-side of the supply is switched in) udg-98053
10 ucc1921 ucc2921 ucc3921 unitrode corporation 7 continental blvd. ? merrimack, nh 03054 tel. (603) 424-2410 ? fax (603) 424-3460 w figure 8. floating positive application the ground-side of the supply is switched in application information (continued) udg-98054
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples ucc2921d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ucc2921 ucc2921dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ucc2921 ucc2921dtr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ucc2921 ucc2921dtrg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 ucc2921 ucc3921d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ucc3921 ucc3921d/81143 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ucc3921 ucc3921d/81143g4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ucc3921 ucc3921dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ucc3921 ucc3921dtr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ucc3921 ucc3921dtr/81143 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ucc3921 ucc3921dtr/81143g4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ucc3921 ucc3921dtrg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ucc3921 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined.
package option addendum www.ti.com 11-apr-2013 addendum-page 2 pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ucc2921dtr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 ucc3921dtr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 ucc3921dtr/81143 soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 package materials information www.ti.com 31-dec-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ucc2921dtr soic d 8 2500 367.0 367.0 35.0 ucc3921dtr soic d 8 2500 367.0 367.0 35.0 ucc3921dtr/81143 soic d 8 2500 367.0 367.0 35.0 package materials information www.ti.com 31-dec-2012 pack materials-page 2

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